Embodiments of the present invention relate to an electrical circuit for signal processing and a method for signal processing.
A signal processing may, for example, be understood as an analog-to-digital conversion or a digital-to-analog conversion but also as a digital-to-digital conversion. A circuit technology often used in analog-to-digital converters and digital-to-analog converters is based on the so-called delta-sigma modulation (DSM). To avoid unwanted effects in sigma-delta converters, like cyclic repetitions of the output pattern, they are operated with a reset between the measurement values (i.e. incrementally), for example. Further, in FFT (fast Fourier transformation) so-called leakage effects may occur when a signal of the FFT is considered to be periodic but no integer number of periods of the signal is included in the time window considered.
There are different approaches to avoid these effects. According to a first approach, time weighting of window functions is applied, which has the tendency to only attenuate the side lines but not to (systematically) avoid them. A further approach is based on the synchronization of system frequencies relative to a reference frequency using a phase-locked loop (PLL), for example. One application example is measurement technology. PLLs are used in measurement technology to adapt the sampling rate (rate of pickup of measurement values) to a defined period of a periodic signal to be measured, for example. In detail, the system frequency or sampling frequency, of a controlled oscillator is adapted to the signal to be measured with the aid of the phase-locked loop such that sampling rate to reference frequency synchronization is accomplished by means of the PLLs.
The Patent Application DE 2012 003909 concerns sigma-delta-analog-to-digital converters in which an integrator adds up decimated sampling values over a predetermined number of decimation sampling values. Upon triggering by the integration counter, the integration value obtained through the integration over the predetermined number of decimation sampling rates is transferred to the integrator output shadow, the integrator is reset and the integration starts anew.
Below, this mechanism will be explained on the basis of an example in combination with the resulting drawbacks. In an alternating voltage three-phase system, the electrical quantities current and voltage are to be measured. The measurement is to be accomplished with a common sampling rate or measurement rate of 26=64 measurement values per period, since measurement rates of this scale also allow for a very efficient fast Fourier transformation algorithm (FFT algorithm). It is assumed that the system clock of the measurement setup is in the range of about 8 MHz to be able to ideally operate the sigma-delta modulation used for the analog-to-digital conversion. Regarding technical implementation, a PLL may be used here, which takes every 64th sampling value as representation of the phase error. If, for example, the phase of the controlled oscillator lags behind, e.g. because the output frequency is too low, a sampling value >0 results. In the reverse case, when the phase is leading, the sampling rate is <0. These deviations from the set point “0” may be detected through the determination of the phase error so that a respective correction is possible. However, the drawback here is that especially in applications on supply mains with low frequencies (50 Hz, 60 Hz or 16⅔ Hz), a high division factor between system clock (8 MHz) and reference clock (50 Hz, 60 Hz or 16⅔ Hz) results. Depending on the application, it is in the range of 1.3×105 (8 MHz/60 Hz) and 4.8×105 (8 MHz/16.7 Hz). As a result, the regulation may become very slow, while, on the other hand, an even more finely resolved frequency setting has to be allowed by the controllable oscillator, which does not let the regulator deviation become too large from one phase comparison to a next. However, such finely adjustable oscillators have a high need for space and power. Therefore, there is need for an improved approach.
It is the object of the present invention to provide a concept for efficient readjustment of a signal processing chain without a controllable oscillator.